1. Field of the Invention
This invention relates to a semiconductor memory device with a current-sensing type of sense amplifier.
2. Description of the Related Art
EEPROM flash memories are classified in general into NAND-type and NOR-type ones. A NAND-type flash memory is formed of NAND strings (i.e., NAND cell units) each having plural memory cells connected in series in such a way that adjacent cells share a source/drain diffusion layer. Therefore, the cell density is made higher than that of a NOR-type one. Besides the NAND-type flash memory has a feature with low power consumption because plural memory cells may be written in a lump by use of FN tunnel current. Considering these features, the NAND-type flash memory is mainly applied to a file memory with a large capacity.
By contrast, since a NOR-type flash memory has, in spite of the large power consumption, a possibility of high speed access, it is mainly applied to mobile apparatuses.
Recently, however, a mobile apparatus tends to deal with an image data and the like with a large quantity of data. Therefore it is required of the mobile apparatus to contain a flash memory which has a high-speed performance and a large capacity with the same level as a file memory. Accordingly, to adapt a NAND-type flash memory to a high-speed system with a buffer memory such as DRAMs, there has been provided a method of improving the data transmission rate, in which, for example, cell data is read out to a page buffer and then serially transferred and output.
Even the above-described method is used, there is a limit for improving the speed of the NAND-type flash memory because cell current thereof is one several tenth of that of a NOR-type flash memory, so that it is difficult to sense data at a high rate as in the NOR-type flash memory with a reference level. The sense amplifier used in a NAND-type flash memory sensing cell data with detecting whether the bit line voltage is discharged or not in accordance with cell data, it takes a time by the micro second for data-sensing.
For the purpose of making possible to store a large quantity of data, there has been provided a flash memory with a multi-value data storage scheme. Further, there has been provided a method of reducing the read time by reducing the read number in the multi-value data storage scheme (for example, refer to JP-P2001-93288A).
Further, there has been provided a memory device with a multi-level data storage scheme, in which two memory cells connected to a pair of bit lines constitute a pair cell, and multi-level data is stored as been defined by a combination of different threshold voltages in the pair cell (for example, refer to JP-P2003-111960A).